Test Bank Answers Chapter.9 Main Memory

Chapter 9

Multiple Choice Questions

1. Computing systems need cache because

A) accessing main memory is slow and cache speeds it up.

B) register access is slow and cache speeds it up.

C) main memory is expensive and cache offsets the cost.

D) All of the about.

Feedback: 9.1.1

Difficulty: Easy

2. Which of the following statement is correct?

A) Base register holds the size of a process.

B) Limit register holds the size of a process.

C) Base and limit registers can be loaded by the standard load instructions in the instruction set.

D) Any attempt by a user program to access memory at an address higher than the base register value results in a trap to the operating system.

Feedback: 9.1.1

Difficulty: Medium

3. If the base register is loaded with value 12345 and limit register is loaded with value 1000, which of the following memory address access will not result in a trap to the operating system?

A) 12500

B) 12200

C) 13346

D) 12344

Feedback: 9.1.1

Difficulty: Easy

4. Assume the value of the base and limit registers are 1200 and 350 respectively. Which of the following addresses is legal?

A) 355

B) 1200

C) 1551

D) all of the above

Feedback: 9.1.1

Difficulty: Easy

5. _____ is the method of binding instructions and data to memory performed by most general-purpose operating systems.

A) Interrupt binding

B) Compile time binding

C) Execution time binding

D) Load-time binding

Feedback: 9.1.2

Difficulty: Medium

6. If the starting address location changes, in which of the following cases, the program has to be recompiled?

A) Execution time binding.

B) Load time binding.

C) Compile time binding

D) Both compile and load time bindings.

Feedback: 9.1.2

Difficulty: Easy

7. If execution time binding is used,

A) logical addresses of process may change over time but physical addresses remain the same.

B) physical addresses of process may change over time but logical addresses remain the same.

C) both physical and logical addresses may change over time.

D) both physical and logical addresses remain the same over time.

Feedback: 9.1.3

Difficulty: Medium

8. Suppose the size of a process is 10,000 bytes and the relocation register is loaded with value 5000, which of the following memory address this process can access?

A) logical address 10,350

B) physical address 4,500

C) physical address 10,350

D) None of the above

Feedback: 9.1.3

Difficulty: Easy

9. An address generated by a CPU is referred to as a ____.

A) physical address

B) logical address

C) post relocation register address

D) Memory-Management Unit (MMU) generated address

Feedback: 9.1.3

Difficulty: Easy

10. Suppose a program is operating with execution-time binding and the physical address generated is 300. The relocation register is set to 100. What is the corresponding logical address?

A) 199

B) 201

C) 200

D) 300

Feedback: 9.1.3

Difficulty: Easy

11. Which of the following is true about dynamic storage allocation?

A) Worst fit provides the best storage utilization.

B) First fit requires less time for allocation than worst fit on average.

C) Best fit is clearly better than first fit in terms of time and storage utilization.

D) First fit is clearly better than best fit in terms of time and storage utilization.

Feedback: 9.2.2

Difficulty: Difficult

12. External fragmentation is

A) when there is some unused memory that cannot be allocated to a process.

B) when the amount of available memory is less than the size of a process.

C) when a process is broken up into smaller parts for memory allocation.

D) when there is enough total memory space to satisfy a request but the available spaces are not contiguous.

Feedback: 9.2.3

Difficulty: Medium

13. Consider a logical address with 18 bits used to represent an entry in a conventional page table. How many entries are in the conventional page table?

A) 262,144

B) 1,024

C) 1,048,576

D) 18

Feedback: 9.3.1

Difficulty: Easy

14. Given the logical address 0xAEF9 (in hexadecimal) with a page size of 256 bytes, what is the page number?

A) 0xAE

B) 0xF9

C) 0xA

D) 0x00F9

Feedback: 9.3.1

Difficulty: Medium

15. A large page size results in

A) lower internal fragmentation

B) larger page table overhead

C) efficient disk I/O

D) All of the above

Feedback: 9.3.1

Difficulty: Medium

16. A frame table stores

A) which frames are allocated.

B) which frames are free.

C) total number of frames.

D) All of the above.

Feedback: 9.3.1

Difficulty: Easy

17. A(n) ______ matches the process with each entry in the TLB.

A) address-space identifier

B) process id

C) stack

D) page number

Feedback: 9.3.2

Difficulty: Medium

18. A page-table base register stores

A) a pointer to the page table in memory.

B) the starting logical address of the page currently being accessed.

C) the starting physical address of the frame currently being addressed.

D) the page size of the page currently being accessed.

Feedback: 9.3.2

Difficulty: Easy

19. A translation look-aside buffer is used to

A) cache page table entries.

B) store the address of the page table in memory.

C) size of the logical address space of the currently running process.

D store page size.

Feedback: 9.3.2

Difficulty: Easy

20. The protection bit in a page table

A) provides protection against unauthorized updates in the page table.

B) marks a page table as read-only or read-write.

C) marks a frame as read-only or read-write.

D) All of the above.

Feedback: 9.3.3

Difficulty: Easy

21. Reentrant code is easier to share when paging is used, because

A) each process can modify that code its own way.

B) the code doesn’t change during execution.

C) the code changes are identical for each process.

D) All of the above.

Feedback: 9.3.4

Difficulty: Easy

22. Assume a system uses 2-level paging and has a TLB hit ratio of 90%. It requires 15 nanoseconds to access the TLB, and 85 nanoseconds to access main memory. What is the effective memory access time in nanoseconds for this system?

A) 22

B) 108.5

C) 30.5

D) 117

Feedback: 9.4.1

Difficulty: Difficult

23. Which of the following technique is well suited to support very large address space, e.g. 64-bit address space?

A) Inverted page tables

B) Hierarchical page tables

C) Clustered page tables

D) All of the above

Feedback: 9.4.2

Difficulty: Medium

24. The _____ binding scheme facilitates swapping.

A) interrupt time

B) load time

C) assembly time

D) execution time

Feedback: 9.5

Difficulty: Medium

25. The roll out, roll in variant of swapping is used ____.

A) when a backing store is not necessary

B) for the round-robin scheduling algorithm

C) for priority-based scheduling algorithms

D) when the load on the system has temporarily been reduced

Feedback: 9.5

Difficulty: Medium

26. A page out operation

A) moves a page from memory to the backing store.

B) moves a page from the backing store to memory.

C) moves a page from one frame to another.

D) deletes a page from the backing store.

Feedback: 9.5.2

Difficulty: Easy

27. Replacement question: With segmentation in IA-32 architecture, a logical address consists of _____.

A) segment number and offset

B) segment number, GDT or LDT indicator, protection and offset

C) segment number, page number and offset

D) segment number, page number, GDT/LDT, protection and offset

Feedback: 9.6.1

Difficulty: Easy

28. Replacement Question: Address translation from a logical address to a physical address in IA-32 architecture is comprised of

A) a segmentation unit that translates the logical address to its physical address.

B) a paging unit that translates the logical address to its physical address.

C) a segmentation unit followed by a paging unit that translate the logical address to its physical address.

D) a paging unit followed by a segmentation unit that translates the logical address to its physical address.

Feedback: 9.6.1

Difficulty: Easy

29. The x86-64 architecture provides support for

A) 64-bit physical addresses

B) 48-bit physical addresses

C) 32-bit physical addresses

D) 52-bit physical addresses

Feedback: 9.6.2

Difficulty: Medium

30. The x86-64 architecture provides support for

A) three different page sizes using 3-level paging hierarchy.

B) four different page sizes using 4-level paging hierarchy.

C) four different page sizes using 3-level paging hierarchy.

D) three different page sizes using 4-level paging hierarchy.

Feedback: 9.6.2

Difficulty: Easy

31. A 64-bit architecture with more than 16 quintillion addressable memory

A) can support a majority of today’s application requirements, but not all.

B) is large enough to support all current as well as future application requirements.

C) is large enough to support all current application requirements but may not be able to support all future application requirements.

D) All of the above.

Feedback: 9.7

Difficulty: Medium

Essay Questions

1. How is a limit register used for protecting main memory?

Feedback: 9.1.1

Difficulty: Medium

2. What is the advantage of using dynamic loading?

Feedback: 9.1.4

Difficulty: Medium

3. When does external fragmentation occur?

Feedback: 9.2.2

Difficulty: Medium

4. Distinguish between internal and external fragmentation.

Feedback: 9.2.2

Difficulty: Medium

5. Explain the basic method for implementing paging.

Feedback: 9.3.1

Difficulty: Medium

6. Using Figure 9.12, describe how a logical address is translated to a physical address.

Feedback: 9.3.2

Difficulty: Medium

7. Describe how a transaction look-aside buffer (TLB) assists in the translation of a logical address to a physical address.

Feedback: 9.3.2

Difficulty: Medium

8. How are illegal page addresses recognized and trapped by the operating system?

Feedback: 9.3.3

Difficulty: Medium

9. Describe the elements of a hashed page table.

Feedback: 9.4.2

Difficulty: Difficult

10. What is the context switch time, associated with swapping, if a disk drive with a transfer rate of 2 MB/s is used to swap out part of a process that is 200 KB in size? Assume that no seeks are necessary and that the average latency is 15 ms. The time should reflect only the amount of time necessary to swap out the process.

Feedback: 9.5

Difficulty: Medium

11. Explain why mobile operating systems generally do not support paging.

Feedback: 9.5.3

Difficulty: Medium

12. Replacement questions: Briefly describe the memory management scheme of IA-32. How does it differ from the paging memory management scheme in terms of the user's view of memory?

In contrast, in a paging scheme, the user specifies a single logical address, which is partitioned by the hardware into a page number and an offset, all invisible to the programmer.

Feedback: 9.6.1

Difficulty: Medium

13. Describe the partitions in a logical-address space of a process in the IA-32 architecture.

Feedback: 9.6.1

Difficulty: Difficult

14. Using Figure 9.26, describe how address translation is performed on ARM architectures.

Feedback: 9.7

Difficulty: Medium

True/False Questions

1. A relocation register is used to check for invalid memory addresses generated by a CPU.

Feedback: 9.1.3

Difficulty: Medium

2. Fragmentation does not occur in a paging system.

Feedback: 9.3

Difficult: Medium

3. A 32-bit logical address with 8 KB page size will have 1,000,000 entries in a conventional page table.

Feedback: 9.3.1

Difficulty: Medium

4. Without a mechanism such as an address-space identifier, the TLB must be flushed during a context switch.

Feedback: 9.3.2

Difficulty: Medium

5. There is a 1:1 correspondence between the number of entries in the TLB and the number of entries in the page table.

Feedback: 9.3.2

Difficulty: Easy

6. Reentrant code cannot be shared.

Feedback: 9.3.4

Difficulty: Easy

7. Hierarchical page tables are appropriate for 64-bit architectures.

Feedback: 9.4.1

Difficulty: Medium

8. Hashed page tables are particularly useful for processes with sparse address spaces.

Feedback: 9.4.2

Difficulty: Easy

9. Hashed page tables are commonly used when handling addresses larger than 32 bits.

Feedback: 9.4.2

Difficulty: Easy

10. Inverted page tables require each process to have its own page table.

Feedback: 9.4.3

Difficulty: Medium

11. Mobile operating systems typically support swapping.

Feedback: 9.5.3

Difficulty: Easy

12. In swapping with paging technique, individual pages of a process are swapped in or out.

Feedback: 9.5.2

Difficulty: Easy

13. The ARM architecture uses both single-level and two-level paging.

Feedback: 9.7

Difficulty: Medium